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培訓(xùn)方式以講課和實(shí)驗(yàn)穿插進(jìn)行

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Virtuoso Chip Assembly Router Course Description

This course explores the basic design flow for device-level and chip-level routing with?Virtuoso Chip Assembly Router. You will focus on methods of solving typical problems?while routing a top-level block design.

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The highlights of this class include the following:

• Learn about available translators for the Virtuoso Chip Assembly Router
• Find, analyze, and solve typical problems
• Explore component placement techniques
• Understand routing techniques (automatic and interactive)
• Create rules for clearance, timing, and noise
• Explore power routing capabilities
• Route device-level designs
• Route a chip-level design

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Audience

• DSM Designers
• Chip Designers
• The primary audience includes experienced chip assembly users who are interested in improving block and chop assembly routing techniques for their design flows

Prerequisites

Students should already have knowledge of:

• Virtuoso Layout Editor
• Virtuoso XL Layout Editor

Students should have practical experience with:

• UNIX OS

Course Agenda

• Introduction
• Preparing and translating data
• Virtuoso Chip Assembly Router environment
• Interactive placement
• Interactive routing
• Using rules and levels
• How the autorouter works
• Creating device-level designs
• Creating chip-assembly deisgner